The present invention relates to an impedance matching circuit used in semiconductor ICs, such as memory devices, and more particularly to an impedance matching circuit with a ZQ calibration.
Generally, various semiconductor devices implemented by integrated circuits such as CPU's, memories and gate arrays are used for various digital products such as personal computers, servers and work stations. For the most part, semiconductor devices have an input circuit for receiving different signals from an external circuit through input pads and an output circuit for providing internal signals to the external circuit.
As the operation speed of digital products becomes higher, the swing width of the signals which are interfaced between semiconductor devices is decreased. The reason why the swing width is getting narrower is that it is necessary to minimize the transmission time of the signals. However, the narrower the swing width is, the more the semiconductor devices are influenced by the external noise and the more serious the echo-back signal caused by impedance mismatching at the interface. Impedance mismatching is generated by external noise, a change of power supply voltage or temperature or a change in the manufacturing process. If impedance mismatching is created, it is difficult to transmit the data at a high speed and the output data from an output terminal of the semiconductor device can be distorted. Therefore, in the case where the semiconductor device at the receiving side receives the distorted output signal through its input terminal, problems such as setup/hold failure or misjudgment can be caused frequently. Semiconductor devices, in which high speed operation is required employ an impedance matching circuit in the vicinity of a pad within the integrated circuit chip to attempt to solve these problems.
A ZQ calibration refers to a process of producing pull-up and pull-down codes based on the fluctuations of the PVT (process, voltage, and temperature) conditions. The resistances (termination resistance of a DQ pad in case of a memory device) of input and output circuits are controlled by using the codes which are caused by the result of the ZQ calibration.
Hereinafter, a ZQ calibration circuit performing the ZQ calibration will be described FIG. 1 is a block diagram of a conventional ZQ calibration circuit. The conventional ZQ calibration circuit includes a first pull-up resistance unit 110, a second pull-up resistance unit 120, a pull-down resistance unit 130, a reference voltage generator 102, comparators 103 and 104, and pull-up and pull-down counters 105 and 106.
A supply voltage VDDQ is divided by the first pull-up resistance unit 110 and a reference resistor 101, thereby providing a ZQ voltage to a node ZQ. The reference resistor 101 connected to a pad ZQ coupled to the node ZQ typically has resistance of 240Ω. The comparator 103 compares the ZQ voltage to a reference voltage VREF (typically, set to VDDQ/2), which is produced by the reference voltage generator 102, and then produces up/down signals using the comparison result.
The pull-up counter 105 receives the up/down signals and then produces a binary code PCODE<0:N>. The resistance value of the first pull-up resistance unit 110 is controlled by a switching operation of resistors through the binary code PCODE<0:N>. The controlled resistance value of the pull-up resistance unit 110 influences the node ZQ and this operation is repeated. In other words, the first pull-up resistance unit 110 undergoes calibration so that the total resistance value of the first pull-up resistance unit 110 is the same as the resistance value of the reference resistance 101 (typically 240Ω), which is called a pull-up calibration.
A pull-up calibration code PCODE<0:N> generated by the pull-up calibration process is inputted to the second pull-up resistance unit 120, thereby determining the total resistance of the second pull-up resistance unit 120. Because the second pull-up resistance unit 120 has the same configuration as the first pull-up resistance unit 110, it has the same resistance value as the first pull-up resistance unit 110 in response to the same code. Similar to pull-up calibration, pull-down calibration starts in such a manner that a voltage on a node A becomes the same as the reference voltage VREF by using the comparator 104 and the pull-down counter 106. In other words, the total resistance value of the pull-down resistance unit 130 becomes the same as that of the second pull-up resistance unit 120, thereby generating a pull down code NCODE<0:N>, which is called a pull-down calibration.
The pull-up calibration code PCODE<0:N> and the pull-down calibration code NCODE<0:N>, which are generated as the result of the ZQ calibration, are inputted into pull-up and pull-down termination resistance units (which are identical to the pull-up and pull-down resistance unit of the ZQ calibration unit) of the input/output terminal (the DQ pad in case of the memory device) of the semiconductor device and it then decides the termination resistance value (not shown).
Since the ZQ calibration is performed based on the codes of N+1, it has problems in that a mismatch exists between the external resistor 101 and the first pull-up resistance unit 110 according to the value of N and another mismatch also exists between the second pull-up resistance unit 120 and the pull-down resistance unit 130.
Moreover, in case of the pull-down calibration, there is a problem in that a mismatch between the external resistor 101 and the pull-down resistance unit 130 is enlarged as a total of the mismatch between the external resistor 101 and the first pull-up resistance unit 110 and the mismatch between the second pull-up resistance unit 120 and the pull-down resistance unit 130.
FIG. 2 is a timing chart of an operation in which voltages on nodes ZQ and A follow a voltage waveform of a reference voltage (1/2VDDQ) based on a ZQ calibration. Because the reference voltage (1/2VSSQ) is different from the ZQ voltage on the node ZQ, the resistance value of the first pull-up resistance unit 110 is different from that of the external resistor 101. Because the reference voltage (1/2VDDQ) is different from the voltage on the node A, the resistance value of the second pull-up resistance unit 120 is different from that of the pull-down resistance unit 130. Accordingly, such the mismatch can be shown in FIG. 2.